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dual output synchronous buck pwm controller adp1877 rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009C2010 analog devices, inc. all rights reserved. features input voltage range: 2.75 v to 14.5 v output voltage range: 0.6 v to 90% v in maximum output current greater than 25 a per channel programmable frequency: 200 khz to 1.5 mhz flex-mode architecture with integrated drivers 180 phase shift minimizes input ripple current and required input capacitance 0.85% output voltage accuracy ?40c to +85c integrated boost diodes pulse skip high efficiency mode under light load power good with internal pull-up resistor overvoltage and overcurrent limit protection thermal overload protection input undervoltage lockout (uvlo) externally adjustable soft start, slope compensation and current sense gain independent precision enable inputs synchronization input suitable for any output capacitors available in 32-lead 5 mm 5 mm lfcsp applications set top boxes printers communication infrastructure distributor power dc systems industrial and instrumentation general description the adp1877 is a flex-mode? (proprietary architecture of analog devices, inc.), dual-channel, step-down switching controller with integrated drivers that drive n-channel synchronous power mosfets. the two pwm outputs are phase shifted 180, which reduces the input rms current, thus minimizing required input capacitance. the boost diodes are built into the adp1877, thus lowering the overall system cost and component count. the adp1877 can be set to operate in pulse skip high efficiency mode under light load or in pwm continuous conduction mode. the adp1877 includes externally adjustable soft start, output overvoltage protection, externally adjustable current limit, power good, and a programmable oscillator frequency that ranges from 200 khz to 1.5 mhz. the adp1877 provides an output voltage accuracy of 0.85% from ?40c to +85c and 1.5% from ?40c to 125c in junction temperature. this part can be powered from a 2.75 v to 14.5 v supply, operates over the ?40 o c to +125 o c junction temperature range, and is availa- ble in a 32-lead 5 mm 5 mm lfcsp package. ramp1 r amp1 vin dh1 bst1 sw1 ilim1 fb1 dl1 pgnd1 ramp2 dh2 bst2 sw2 ilim2 fb2 dl2 pgnd2 en1 en2 vdl vcco pgood1 pgood2 trk1 trk2 sync freq comp1 comp2 ss1 ss2 agnd r csg1 r top1 m1 m2 r bot1 r csg2 r top2 m3 l2 l1 vout1 vout2 vin v in m4 r bot2 r ramp2 08299-001 figure 1. typical operation circuit 0.01 0.1 1 10 100 0 10 20 30 40 50 60 70 80 90 100 v o = 3.3v psm v o = 3.3v pwm v o = 1.8v psm v o = 1.8v pwm v in = 12v, 300khz 08299-002 efficiency (%) load (a) figure 2. efficiency plot of figure 42 , 20 a output
adp1877 rev. c | page 2 of 3 2 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? absolute maximum ratings ............................................................ 6 ? esd caution .................................................................................. 6 ? simplified block diagram ............................................................... 7 ? pin configuration and function descriptions ............................. 8 ? typical performance characteristics ........................................... 10 ? theory of operation ...................................................................... 13 ? control architecture .................................................................. 13 ? oscillator fr equency .................................................................. 13 ? mode of operation ..................................................................... 14 ? synchronization .......................................................................... 14 ? soft start ...................................................................................... 14 ? synchronous rectifier and dead time ................................... 15 ? input undervoltage lockout ..................................................... 15 ? internal linear regulator .......................................................... 15 ? overvoltage protection .............................................................. 15 ? power good ................................................................................. 15 ? short circuit and current limit protection ........................... 16 ? shutdown control ...................................................................... 16 ? thermal overload protection ................................................... 16 ? applications information .............................................................. 17 ? setting the output voltage ........................................................ 17 ? soft start ...................................................................................... 17 ? setting the current limit .......................................................... 17 ? accurate current limit sensing ............................................... 17 ? setting the slope compensation .............................................. 18 ? setting the current sense gain ................................................ 18 ? input capacitor selection .......................................................... 19 ? input filter ................................................................................... 19 ? boost capacitor selection ......................................................... 20 ? inductor selection ...................................................................... 20 ? output capacitor selection ....................................................... 20 ? mosfet selection ..................................................................... 21 ? loop compensation .................................................................. 22 ? switching noise and overshoot reduction ............................ 23 ? voltage tracking ......................................................................... 23 ? coincident tracking .................................................................. 23 ? ratiometric tracking ................................................................. 24 ? pcb layout guideline ................................................................... 25 ? mosfets, input bulk capacitor, and bypass capacitor ...... 25 ? high current and current sense paths ................................... 25 ? signal paths ................................................................................. 25 ? pgnd plane ................................................................................ 25 ? feedback and current limit sense paths ............................... 25 ? switch node ................................................................................ 26 ? gate driver paths ....................................................................... 26 ? output capacitors ...................................................................... 26 ? typical operating circuits ............................................................ 27 ? outline dimensions ....................................................................... 31 ? ordering guide .......................................................................... 31 ? revision history 4/10rev. b to rev. c changes to features and general description ............................. 1 changes to quiescent current parameter and fb to trk offset voltage parameter, table 1 .............................................................. 3 changes to theory of operation section .................................... 13 changes to setting the slope compensation section ................ 18 11/09rev. a to rev. b changes to product title ................................................................. 1 changes to signal path section .................................................... 25 9/09rev. 0 to rev. a changes to features section, general description section, and figure 2 ............................................................................................... 1 changes to output characteristics, feedback accuracy voltage parameter; error amplifier, transconductance parameter; and linear regulator, vcco load regulation and vin to vcco dropout voltage parameters, table 1 ............................................. 3 changes to pin 4, pin 16, and pin 25 descriptions, table 3 ........ 8 changes to figure 5 and figure 6 ................................................. 10 9/09revision 0: initial version
adp1877 rev. c | page 3 of 3 2 specifications all limits at temperature extremes are guaranteed via correlation using standard statistical quality control. v in = 12 v. the specifications are valid for t j = ?40c to +125c, unless otherwise specified. typical values are at t a = 25c. table 1. parameter symbol conditions min typ max unit power supply input voltage v in 2.75 14.5 v undervoltage lockout threshold in uvlo v in rising 2.45 2.6 2.75 v v in falling 2.4 2.5 2.6 undervoltage lockout hysteresis 0.1 v quiescent current i in en1 = en2 = v in = 12 v, v fb = v cco in pwm mode (no switching) 4.5 5.8 ma shutdown current i in_sd en1 = en2 = gnd, v in = 5.5 v or 14.5 v 100 200 a error amplifier fb input bias current i fb ?100 +1 +100 na transconductance g m sink or source 1 a, t a = 25 o c 440 550 660 s sink or source 1 a 385 550 715 s trk1, trk2 input bias current i trk 0 v < v trk1/trk2 < 1.5 v ?100 +1 +100 na current sense amplifier gain a cs gain resistor connected to dl, r csg = 47 k 5% 2.4 3 3.6 v/v gain resistor connected to dl, r csg = 22 k 5% 5.2 6 6.9 v/v default setting, r csg = open 10.5 12 13.5 v/v gain resistor connected to dl, r csg = 100 k 5% 20.5 24 26.5 v/v output characterictistics feedback accuracy voltage v fb t j = ?40 c to +85 c, v fb = 0.6 v ?0.85% +0.6 +0.85% v t j = ?40 c to +125 c, v fb = 0.6 v ?1.5% +0.6 +1.5% v line regulation of pwm v fb /v in 0.015 %/v load regulation of pwm v fb /v comp v comp range 0.9 v to 2.2 v 0.3 % oscillator frequency f osc r freq = 340 k to agnd 170 200 235 khz r freq = 78.7 k to agnd 744 800 856 khz r freq = 39.2 k to agnd 1275 1500 1725 khz freq to agnd 235 300 345 khz freq to vcco 475 600 690 khz sync input frequency range f sync f sync = 2 f sw ; f sync = f osc ; the minimum sync frequency is 1 the f osc set by the resistor 400 3000 khz sync input pulse width t syncmin 100 ns sync pin capacitance to gnd c sync 5 pf linear regulator vcco output voltage t a = 25c, i vcco = 100 ma 4.8 5.0 5.18 v t j = ?40 c to +125 c 4.7 5.0 5.3 v vcco load regulation i vcco = 0 ma to 100 ma, 35 mv vcco line regulation v in = 5.5 v to 14.5 v, i vcco = 20 ma 10 mv vcco current limit 1 vcco drops to 4 v from 5 v 350 ma vcco short-circuit current 1 vcco < 0.5 v 370 400 ma vin to vcco dropout voltage 2 v dropout i vcco = 100 ma, v in 5 v 0.33 v
adp1877 rev. c | page 4 of 32 parameter symbol conditions min typ max unit logic inputs en1, en2 en1/en2 rising 0.57 0.63 0.68 v en1, en2 hysteresis 0.03 v en1, en2 input leakage current i en v in = 2.75 v to 14.5 v 1 200 na sync logic input low 1.3 v sync logic input high 1.9 v sync input leakage current i sync sync = 5 v, internal 1 m pull-down 5 6.5 a gate drivers dh rise time c dh = 3 nf, v bst ? v sw = 5 v 16 ns dh fall time c dh = 3 nf, v bst ? v sw = 5 v 14 ns dl rise time c dl = 3 nf 16 ns dl fall time c dl = 3 nf 14 ns dh to dl dead time external 3 nf is connected to dh and dl 25 ns dh or dl driver r on , sourcing current 1 r on_sourc sourcing 2 a with a 100 ns pulse 2 sourcing 1 a with a 100 ns pulse, v in = 3 v 2.3 dh or dl driver r on , tempco tc ron v in = 3 v or 12 v 0.3 %/ o c dh or dl driver r on , sinking current 1 r on_sink sinking 2 a with a 100 ns pulse 1.5 sinking 1 a with a 100 ns pulse, v in = 3 v 2 dh maximum duty cycle f osc = 300 khz 90 % dh maximum duty cycle f osc = 1500 khz 50 % minimum dh on time f osc = 200 khz to 1500 khz 130 ns minimum dh off time f osc = 200 khz to 1500 khz 330 ns minimum dl on time f osc = 200 khz to 1500 khz 280 ns comp voltage range comp pulse skip threshold v comp,thres in pulse skip mode 0.9 v comp clamp high voltage v comp,high 2.25 v thermal shutdown thermal shutdown threshold t tmsd 155 c thermal shutdown hysteresis 20 c overvoltage and power good thresholds fb overvoltage threshold v ov v fb rising 0.67 0.7 0.73 v fb overvoltage hysteresis 40 mv fb undervoltage threshold v uv v fb rising 0.51 0.54 0.57 v fb undervoltage hysteresis 30 mv trk input voltage range 0 5 v fb to trk offset voltage trk = 0.5 v to 0.6 v; offset = v fb ? v trk ?120 ?70 ?5 mv soft start ss output current i ss during start-up 4.6 6.5 8.4 a ss pull-down resistor during a fault condition 1 k
adp1877 rev. c | page 5 of 32 parameter symbol conditions min typ max unit pgood pgood pull-up resistor r pgood internal pull-up resistor to vcco 12.5 k pgood delay 12 s overvoltage or undervoltage this is the minimum duration required to trip the pgood signal. 12 s minimum duration ilim1, ilim2 threshold voltage 1 relative to pgnd ?5 0 +5 mv ilim1, ilim2 output current ilim = pgnd 40 50 60 a current sense blanking period after dl goes high, current limit is not sensed during this period. 100 ns integrated rectifier (boost diode) resistance at 20 ma forward current 16 zero current cross offset (sw to pgnd) 1 in pulse skip mode only; f osc = 600 khz 0 2 4 mv 1 guaranteed by design. 2 connect v in to vcco when v in < 5.5 v. for applications with v in < 5.5 v and v in not connected to vcco, keep in mind that vcco = v in ? vdropout. vcco must be 2.75 v for proper operation.
adp1877 rev. c | page 6 of 32 absolute maximum ratings table 2. parameter rating vin, en1/en2, ramp1/ramp2 15 v fb1/fb2, comp1/comp2, ss1/ss2, trk1/trk2, freq, sync, vcco, vdl, pgood1/pgood2 ?0.3 v to +6 v ilim1/ilim2 ?0.3 v to +16 v bst1/bst2, dh1/dh2, sw1/sw2 to pgnd1/pgnd2 ?0.3 v to +22 v dl1/dl2 to pgnd1/pgnd2 ?0.3 v to vcco + 0.3 v bst1/bst2 to pgnd1/pgnd2, sw1/sw2 to pgnd1/pgnd2 20 ns transients +25 v dl1/dl2, sw1/sw2, ilim1/ilim2 to pgnd1/pgnd2 20 ns negative transients ?8 v pgnd1/pgnd2 to agnd ?0.3 v to +0.3 v pgnd1/pgnd2 to agnd 20 ns transients ?8 v to +4 v ja , =on a multilayer pcb (natural convection) 1, 2 32.6c/w operating ambient temperature range 3 ?40c to +85c operating junction temperature range 3 ?40c to +125c storage temperature range ?65c to +150c maximum soldering lead temperature 260c 1 measured with exposed pad attached to pcb. 2 junction-to-ambient thermal resistance ( ja ) of the package was calculated or simulated on a multilayer pcb. 3 the device can be damaged when the junction temperature limits are exceeded. monitoring ambient temperature does not guarantee that t j is within the specified temperature limit s. in applications with moderate power dissipation and low pcb ther mal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. the junction temperature, t j , of the device is dependent on the ambient temperature, t a , the power dissipation of the device, p d , and the junction to ambient thermal resistance of the package, ja . maximum junction temperature is calculated from the ambient temperature and power dissip ation using the formula t j = t a + p d ja . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. unless otherwise specified all other voltages are referenced to gnd. esd caution
adp1877 rev. c | page 7 of 32 simplified block diagram 0 8299-003 duplicate for channel 2 bst1 pgnd1 + ? + ? + ? + ? + ? + ? fb1 0.6v ov uv pgood1 current sense amplifier dh1 dl1 ilim1 sw1 v r e f = 0 . 6 v 6.5a + + ? error amplifier fb1 comp1 ss1 pwm comparator slope comp and ramp generator current limit control vcco ramp1 50a 3.2v g m ov1 + trk1 cs gain driver logic control and state machine over_lim1 pulse skip over_lim1 ldo logic en1 en2 v in uvlo oscillator freq sync ph1 ph2 ref v cco ov uv 0.6v thermal shutdown agnd 0.6v + ? + ? vcco vdl fault ov1 logic over_lim1 ov1 en1 en1_sw logic uv1 1k? 0.9v dcm zero cross detect 10k ? a v = 3, 6, 12, 24 vcco sync dl driver en1_sw en2_sw 1m ? ? + figure 3. block diagram
adp1877 rev. c | page 8 of 32 pin configuration and fu nction descriptions pin 1 indicator 1 en1 2 sync 3 vin 4 vcco 5 vdl 6 a gnd 7 freq 8 en 2 24 sw1 notes 1. connect the bottom exposed pad of the lfcsp package to system agnd plane. 23 dh1 22 pgnd1 21 dl1 20 dl2 19 pgnd2 18 dh2 17 sw2 9 trk 2 10 fb2 11 comp2 12 ramp2 13 ss2 14 pgood2 15 ilim2 16 bst2 32 trk1 31 fb1 30 comp1 29 ramp1 28 ss1 27 pgo od1 26 ilim1 25 bst1 top view (not to scale) adp1877 08299-004 figure 4. pin configuration table 3. pin function descriptions pin o. mnemonic description 1 en1 enable input for channel 1. drive en1 high to turn on th e channel 1 controller, and drive it low to turn off. tie en1 to vin for automatic startup. for a precision uvlo, p ut an appropriately sized resistor divider from vin to agnd, and tie the midpoint to this pin. 2 sync frequency synchronization input. accepts an external signal between 1 and 2.3 of the internal oscillator frequency, f osc , set by the freq pin. the controller operates in fo rced pwm when a signal is detected at sync or when sync is high. the resulting switching frequency is ? of the sync frequency. when sync is low or left floating, the controller operates in pulse skip mode. 3 vin connect to main power supply. bypass with a 1 f or larg er ceramic capacitor connected as close to this pin as possible and pgnd. 4 vcco output of the internal low dropout regulator (ldo). the internal circuitry and gate drivers are powered from vcco. bypass vcco to agnd with a 1 f or larger cera mic capacitor. the vcco output is always active, even during fault conditions and cannot be turned off even if en1/en2 is low. for operations at vin below 5 v, vin can be jumped to vcco. do not use the ldo to power other auxiliary system loads. 5 vdl power supply for the low-side driver. bypass vdl to pgnd with a 1 f or greater ceramic capacitor. connect vcco to vdl. 6 agnd analog ground. 7 freq sets the desired operating frequency between 200 khz an d 1.5 mhz with one resistor between freq and agnd. see table 4 for more details. connect freq to agnd for a preprogrammed 300 khz or freq to vcco for a 600 khz operating frequen cy. 8 en2 enable input for channel 2. drive en2 high to turn on th e channel 2 controller, and drive it low to turn off. tie en2 to vin for automatic startup. for a precision uvlo, p ut an appropriately sized resistor divider from vin to agnd, and tie the midpoint to this pin. 9 trk2 tracking input for channel 2. if the tracking function is not used, it is recommended to connect trk2 to vcco through a resistor higher than 1 m, or simply connect trk2 between 0.7 v and 2 v to reduce the bias current going into the trk2 pin. 10 fb2 output voltage feedback for channel 2. connect to channel 2 via a resistor divider. 11 comp2 compensation node for channel 2. output of channel 2 error amplifier. connect a series resistor-capacitor network from comp2 to agnd to compensate the regulation control loop. 12 ramp2 programmable current setting for slope compensation of channel 2. connect a resistor from ramp2 to vin. the voltage at ramp2 is 0.2 v. 13 ss2 soft start input for channel 2. connect a capacitor from ss2 to agnd to set the soft start period. this node is internally pulled up to 3.2 v through a 6.5 a current source.
adp1877 rev. c | page 9 of 32 pin no. mnemonic description 14 pgood2 open-drain power-good indicator logic output with an internal 12 k resistor connected between pgood2 and vcco. pgood2 is pulled to ground when the channel 2 output is outside the regula tion window. an external pull-up resistor is not required. 15 ilim2 current limit sense comparator inverting input for channel 2. connect a resistor between ilim2 and sw2 to set the current limit offset. for accurate current limit sensing, connect ilim2 to a current sense resistor at the source of the low-side mosfet. 16 bst2 boot strapped upper rail of high side internal driver for channel 2. connect a 0.1 f to a 0.22 f multilayer ceramic capacitor (mlcc) between bst2 and sw2. there is an internal boost rectifier connected between vcco and bst2. 17 sw2 switch node for channel 2. connect to the source of the high-side n-channel mosfet and the drain of the low- side n-channel mosfet of channel 2. 18 dh2 high-side switch gate driver output for channel 2. capa ble of driving mosfets with total input capacitance up to 20 nf. 19 pgnd2 power ground for channel 2. ground for internal channel 2 driver. differential current is sensed between sw2 and pgnd2. it is not recommended to short pgnd2 to pgnd1 directly. 20 dl2 low-side synchronous rectifier gate driver output for cha nnel 2. to set the gain of the current sense amplifier, connect a resistor between dl2 and pgnd2. capable of driv ing mosfets with a total input capacitance up to 20 nf. 21 dl1 low-side synchronous rectifier gate driver output for cha nnel 1. to set the gain of the current sense amplifier, connect a resistor between dl1 and pgnd1. capable of driv ing mosfets with a total input capacitance up to 20 nf. 22 pgnd1 power ground for channel 1. ground for internal channel 1 driver. differential current is sensed between sw1 and pgnd1. it is not recommended to short pgnd2 to pgnd1 directly. 23 dh1 high-side switch gate driver output for channel 1. capa ble of driving mosfets with a total input capacitance up to 20 nf. 24 sw1 power switch node for channel 1. connect to the source of the high-side n-channel mosfet and the drain of the low-side n-channel mosfet of channel 1. 25 bst1 boot strapped upper rail of high side internal driver for channel 1. connect a 0.1 f to a 0.22 f multilayer ceramic capacitor (mlcc) between bst1 and sw1. there is an internal boost diode or rectifier connected between vcco and bst1. 26 ilim1 current limit sense comparator inverting input for channel 1. connect a resistor between ilim1 and sw1 to set the current limit offset. for accurate current limit sensing, connect ilim1 to a current sense resistor at the source of the low-side mosfet. 27 pgood1 power good. open drain power good indicator logic output with an internal 12 k resistor connected between pgood1 and vcco. pgood1 is pulled to ground when th e channel 1 output is outsid e the regulation window. an external pull-up resistor is not required. 28 ss1 soft start input for channel 1. connect a capacitor from ss1 to agnd to set the soft start period. this node is internally pulled up to 3.2 v through a 6.5 a current source. 29 ramp1 programmable current setting for slope compensation of channel 1. connect a resistor from ramp1 to vin. the voltage at ramp1 is 0.2 v during operation. this pin is high impedance when the channel is disabled. 30 comp1 compensation node for channel 1. output of channel 1 error amplifier. connect a series resistor-capacitor network from comp1 to agnd to compensate the regulation control loop. 31 fb1 output voltage feedback for channel 1. connect to channel 1 via a resistor divider. 32 trk1 tracking input for channel 1. if the tracking function is not used, it is recommended to connect trk1 to vcco through a resistor higher than 1 m, or simply connect trk1 between 0.7 v and 2 v to reduce the bias current going into the trk1 pin. 33 bottom exposed pad connect the bottom exposed pad of the lfcsp package to the system agnd plane.
adp1877 rev. c | page 10 of 32 typical performance characteristics 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 efficiency (%) load (a) psm pwm v in = 12v v out = 3.3v 600khz 100 08299-023 figure 5. efficiency plot of figure 41 , 10 a output 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 efficiency (%) load (a) v o = 1.05v_pwm v out = 1.05v psm v o = 1.05v pwm v in = 3v v out = 1.8v pwm v out = 1.8v psm 08299-024 figure 6. efficiency plot of figure 44 , 2 a output ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 5 10 15 20 load regul a tion (%) load (a) v in = 12v v out = 3.3v 0 8299-025 figure 7. load regulation of figure 42 0 0.01 0.02 0.03 0.04 0.05 0.06 6 8 10 12 14 line regul a tion (%) v in (v) v out = 3.3v at 1a load 08299-026 figure 8. line regulation of figure 42 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 2.53.03.54.04.55.0 vcco (v) v in (v) 50ma load 100ma load 08299-027 figure 9. ldo load regulation 4.65 4.70 4.75 4.80 4.85 4.90 4.95 5.00 5.05 5.10 5 7 9 11 13 15 17 vcco (v) v in (v) no load on ldo 100ma load on ldo 08299-028 figure 10. ldo line regulation
adp1877 rev. c | page 11 of 32 0 1 2 3 4 5 6 0123456 vcco (v) v in (v) 08299-029 figure 11. vcco vs. v in ch1 10v ch3 5v ch2 10v m1s a ch1 5.60v sw1 sw2 sync 600khz 08299-035 1 3 2 figure 12. an example of synchronization, f sw = 600 khz ch1 50mv ch4 5a ? m200s a ch4 8.10a output response 5a to 10a step load v in = 12v v out = 1.8v 08299-036 1 4 figure 13. step load transient of figure 42 , 5 a to 10 a ch1 20mv ch4 500ma ? m100s a ch4 750ma v in = 3v v out = 1.8v output response output step load 0.5a to 0.8a 08299-037 1 4 figure 14. step load transient of figure 44 2 ch3 1v ch2 5v ch1 5v ch4 1a ? m1ms a ch1 2.4v v in = 12v v out = 1.8v output precharged to 1v dh1 dl1 vout1 il1 08299-038 1 3 4 figure 15. soft start into precharged output ch3 10v ch2 1v ch1 5v ch4 500mv m2ms a ch2 2.42v en is tied to vin vin power supply v out (ch2) ss sw 08299-039 c ss = 100nf 1 3 2 4 figure 16. power-on sequence
adp1877 rev. c | page 12 of 32 ch3 1v ch2 2v ch1 10v ch4 1v m10ms a ch2 1.52v c ss = 100nf v out (ch3) ss (ch4) en sw 0 8299-040 1 2 3 4 figure 17. enable function ch3 2v ch2 2v ch1 10v ch4 2v ? m10ms a ch2 3.76v sw1 pgood1 vcco (ch3) v out , preloaded (ch4) 0 8299-041 1 2 3 4 figure 18. thermal shutdown waveform ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 2468101214 change in f osc (%) v in (v) 300khz 600khz 850khz reference at v in = 2.75v 08299-030 figure 19. change in f osc vs. v in ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 ?40 ?15 10 35 60 85 110 135 change in f osc (%) temperature (c) v in = 12v; referenced at 25c 0 8299-031 figure 20. f osc vs. temperature 50 100 150 200 250 300 350 2.5 4.5 6.5 8.5 10.5 12.5 14.5 time (ns) v in (v) dh minimum off time dh minimum on time 08299-032 figure 21. typical dh minimum on time and off time ?4 ?3 ?2 ?1 0 1 2 3 4 ?40 ?15 10 35 60 85 110 135 change in minimum on/off time (%) temperature (c) dh minimum on time dh minimum off time 08299-033 figure 22. dh minimum on time and off time overtemperature
adp1877 rev. c | page 13 of 3 2 theory of operation the adp1877 is a current mode (using adi proprietary flex-mode architecture), dual-channel, step-down switching controller with integrated mosfet drivers that drive n-channel synchronous power mosfets. the two outputs are phase shifted 180. this reduces the input rms current, thus minimizing required input capacitance. the adp1877 can be set to operate in pulse skip high efficiency mode under light load or in forced pwm. the integrated boost diodes in the adp1877 reduce the overall system cost and component count. the adp1877 includes programmable soft start, output overvoltage protection, programmable current limit, power good, and tracking function. the adp1877 can be set to operate in any switching frequency between 200 khz and 1.5 mhz with one external resistor. control architecture the adp1877 is based on a fixed frequency current mode pwm control architecture. the inductor current is sensed by the voltage drop measured across the external low-side mosfet r dson during the off period of the switching cycle (valley inductor current). the current sense signal is further processed by the current sense amplifier. the output of the current sense amplifier is held, and the emulated current ramp is multiplexed and fed into the pwm comparator as shown in figure 23 . the valley current information is captured at the end of the off period, and the emulated current ramp is applied at that point when the next on cycle begins. an error amplifier integrates the error between the feedback voltage and the generated the error voltage from the comp pin (from error amp in figure 23 ). ff osc q q s r a cs v cs v in v in a r r ramp i ramp c r from error amp to drivers from low side mosfet 08299-005 figure 23. simplified control architecture as shown in figure 23 , the emulated current ramp is generated inside the ic but offers programmability through the rampx pin. selecting an appropriate value resistor from v in to the ramp pin programs a desired slope compensation value and, at the same time, provides a feed forward feature. the benefits realized by deploying this type of control scheme are that there is no need to worry about the turn-on current spike corrupting the current ramp. also, the current signal is stable because the current signal is sampled at the end of the turn-off period, which gives time for the switch node ringing to settle. other benefits of using current mode control scheme still apply, such as simplicity of loop compensation. control logic enforces antishoot-through operation to limit cross conduction of the internal drivers and external mosfets. oscillator frequency the internal oscillator frequency, which ranges from 200 khz to 1.5 mhz, is set by an external resistor, r freq , at the freq pin. some popular f osc values are shown in tabl e 4 , and a graphical relationship is shown in figure 24 . for instance, a 78.7 k resistor sets the oscillator frequency to 800 khz. furthermore, connecting freq to agnd or freq to vcco sets the oscillator frequency to 300 khz or 600 khz, respectively. for other frequencies that are not listed in table 4 , the values of r freq and f osc can be obtained from figure 24 , or use the following empirical formula to calculate these values: 065.1 )( 96568)( ? = khzf kr osc freq table 4. setting the oscillator frequency r freq f osc (typical) 332 k 200 khz 78.7 k 800 khz 60.4 k 1000 khz 51 k 1200 khz 40.2 k 1500 khz freq to agnd 300 khz freq to vcco 600 khz 10 60 110 160 210 260 310 360 410 100 400 700 1000 1300 1600 1900 r freq (k ? ) f osc (khz) r freq (k ? ) = 96568 f osc (khz) ?1.065 0 8299-034 figure 24. r freq vs. f osc
adp1877 rev. c | page 14 of 32 mode of operation the sync pin is a multifunctional pin. pwm mode is enabled when sync is connected to vcco or a high logic. with sync connected to ground or left floating, pulse skip mode is enabled. switching sync from low to high or high to low on the fly causes the controller to transition from forced pwm to pulse skip mode or pulse skip mode to forced pwm, respectively, in two clock cycles. table 5. mode of operation truth table sync pin mode of operation low pulse skip mode high forced pwm no connect pulse skip mode clock signal forced pwm the adp1877 has a built-in pulse skip sensing circuitry that allows the controller to skip pwm pulses, thus reducing the switching frequency at light loads and, therefore, maintaining high efficiency during a light load operation. the switching frequency is a fraction of the natural oscillator frequency and is automatically adjusted to regulate the output voltage. the resulting output ripple is larger than that of the fixed frequency forced pwm. figure 25 shows that the adp1877 operates in psm under a light load of 10 ma. pulse skip frequency under a certain light load is dependent on the inductor input and output voltages. ch3 20mv ch2 200mv ch1 10v ch4 2a ? m200s a ch1 7.8v sw1 comp1 (ch2) vout ripple inductor current 0 8299-042 1 3 2 4 figure 25. example of pulse skip mode under a light 5 ma load when the output load is greater than the pulse skip threshold current (when v comp reaches the threshold of 0.9 v), the adp1877 exits the pulse skip mode operation and enters the fixed frequency discontinuous conduction mode (dcm), as shown in figure 26 . when the load increases further, the adp1877 enters ccm. ch3 20mv ch2 5v ch1 10v ch4 2a ? m1s a ch1 13.4v dh1 dl1 output ripple inductor current 08299-043 1 2 3 4 figure 26. example of discontinuous conduction mode (dcm) waveform in forced pwm, the adp1877 always operates in ccm at any load. the inductor current is always continuous (and even goes negative when there is no load); thus, efficiency is poor at light loads. synchronization the switching frequency of the adp1877 can be synchronized to an external clock by connecting sync to a clock signal, which should be between 1 and 2.3 of the internal oscillator frequency, f osc . the resulting switching frequency, f sw , is ? of the external sync frequency because the sync input is divided by 2, and the resulting phases are used to clock the two channels alternately. in synchronization, the adp1877 operates in pwm, and f sw equals ? of f sync . when an external clock is detected at the first sync edge, the internal oscillator is reset, and the clock control shifts to sync. the sync edges then trigger subsequent clocking of the pwm outputs. the dh1/dh2 rising edges appear approximately 100 ns after the corresponding sync edge, and the frequency is locked to the external signal. depending on the start-up conditions of channel 1 and channel 2, either channel 1 or channel 2 can be the first channel synchronized to the rising edge of the sync clock. if the external sync signal disappears during operation, the adp1877 reverts to its internal oscillator. when the sync function is used, it is recommended to connect a pull-up resistor from sync to vcco so that when the sync signal is lost, the adp1877 continues to operate in pwm. soft start the soft start period is set by an external capacitor between ss1/ss2 and agnd. when en1/en2 is enabled, a current source of 6.5 a starts charging the capacitor, and the regulation voltage is reached when the voltage at ss1/ss2 reaches 0.6 v. for more information, see the applications information section.
adp1877 rev. c | page 15 of 32 synchronous rectifier and dead time the synchronous rectifier (low-side mosfet) improves efficiency by replacing the schottky diode that is normally used in an asynchronous buck regulator. in the adp1877, the antishoot- through circuit monitors the sw and dl nodes and adjusts the low-side and high-side drivers to ensure break-before-make switching to prevent cross-conduction or shoot-through between the high-side and low-side mosfets. this break-before-make switching is known as the dead time, which is not fixed and depends on how fast the mosfets are turned on and off. in a typical application circuit that uses medium sized mosfets with input capacitance of approximately 3 nf, the typical dead time is approximately 30 ns. when small and fast mosfets are used, the dead time can be as low as 13 ns. input undervoltage lockout when the bias input voltage, v in , is less than the undervoltage lockout (uvlo) threshold, the switch drivers stay inactive. when v in exceeds the uvlo threshold, the switchers start switching. internal linear regulator the internal linear regulator is low dropout (ldo), meaning it can regulate its output voltage, vcco. vcco powers up the internal control circuitry and provides power for the gate drivers. it is guaranteed to have more than 200 ma of output current capability, which is sufficient to handle the gate drive requirements of typical logic threshold mosfets driven at up to 1.5 mhz. vcco is always active and cannot be shut down by the en1/en2 pins. bypass vcco to agnd with a 1 f or greater capacitor. because the ldo supplies the gate drive current, the output of vcco is subject to sharp transient currents as the drivers switch and the boost capacitors recharge during each switching cycle. the ldo has been optimized to handle these transients without overload faults. due to the gate drive loading, using the vcco output for other external auxiliary system load is not recommended. the ldo includes a current limit well above the expected maximum gate drive load. this current limit also includes a short-circuit fold back to further limit the vcco current in the event of a short-circuit fault. the vdl pin provides power to the low-side driver. connect vdl to vcco. bypass vdl to pgnd with a 1 f (minimum) ceramic capacitor, which must be placed close to the vdl pin. for an input voltage less than 5.5 v, it is recommended to bypass the ldo by connecting vin to vcco, as shown in figure 27 , thus eliminating the dropout voltage. however, for example, if the input range is 4 v to 7 v, the ldo cannot be bypassed by shorting vin to vcco because the 7 v input has exceeded the maximum voltage rating of the vcco pin. in this case, use the ldo to drive the internal drivers, but keep in mind that there is a dropout when v in is less than 5 v. vin vcco v in = 2.75v to 5.5 v adp1877 08299-006 figure 27. configuration for v in < 5.5 v overvoltage protection the adp1877 has a built-in circuit for detecting output overvoltage at the fb node. when the fb voltage, v fb , rises above the overvoltage threshold, the low-side nmosfet is immediately turned on, and the high-side nmosfet is turned off until the v fb drops below the undervoltage threshold. this action is known as the crowbar overvoltage protection. if the overvoltage condition is not removed, the controller maintains the feedback voltage between the overvoltage and undervoltage thresholds, and the output is regulated to within approximately +16% and ?10% of the regulation voltage. during an overvoltage event, the ss node discharges toward zero through an internal 1 k pull-down resistor. when the voltage at fb drops below the undervoltage threshold, the soft start sequence restarts. the following graph shows the overvoltage protection scheme in action in psm. ch3 5v ch2 5v ch1 10v ch4 500mv m200s a ch4 2.05v 0 8299-044 1 2 3 dh1 pgood1 vo1 = 1.8v shorted to 2.2v source vin (ch3) 4 figure 28. overvoltage protection in psm power good the pgoodx pin is an open-drain nmos with an internal 12 k pull-up resistor connected between pgoodx and vcco. pgoodx is internally pulled up to vcco during normal operation and is active low when tripped. when the feedback voltage, v fb , rises above the overvoltage threshold or drops below the undervoltage threshold, the pgoodx output is pulled to ground after a delay of 12 s. the overvoltage or undervoltage condition must exist for more than 12 s for pgoodx to become active. the pgoodx output also becomes active if a thermal overload condition is detected.
adp1877 rev. c | page 16 of 32 short circuit and current limit protection shutdown control the en1 and en2 pins are used to enable or disable channel 1 and channel 2, respectively, of the adp1877. the precision enable threshold for en1/en2 is typically 0.63 v. when the en1/en2 voltage rises above 0.63 v, the adp1877 is enabled and starts normal operation after the soft start period. when the voltage at en1/en2 drops below 0.57 v, the switchers and the internal circuits in the adp1877 are turned off. note that en1/en2 cannot shut down the ldo at vcco, which is always active. when the output is shorted or the output current exceeds the current limit set by the r ilim resistor for eight consecutive cycles, the adp1877 shuts off both the high-side and low-side drivers and restarts the soft start sequence every 10 ms, which is known as hiccup mode. the ss node discharges to zero through an internal 1 k resistor during an overcurrent or short-circuit event. figure 29 shows that the adp1877 (a 20 a application circuit) is entering current limit hiccup mode when the output is shorted. for the purpose of start-up power sequencing, the startup of the adp1877 can be programmed by connecting an appropriate resistor divider from the master power supply to the en1/en2 pin, as shown in figure 30 . for instance, if the desired start-up voltage from the master power supply is 10 v, r1 and r2 can be set to 156 k and 10 k, respectively. ch3 500mv ch1 10v ch4 10a ? m2ms a ch1 11.2v sw1 ss1 inductor current 08299-045 1 3 4 v out1 r1 r2 adp1877 en1 or en2 master supply v oltage fb1 or fb 2 r top r bot 08299-007 figure 30. optional power-up sequencing circuit thermal overload protection the adp1877 has an internal temperature sensor that senses the junction temperature of the chip. when the junction temperature of the adp1877 reaches approximately 155c, the adp1877 goes into thermal shutdown, the converter is turned off, and ss discharges toward zero through an internal 1 k resistor. at the same time, vcco discharges to zero. when the junction temperature drops below 135c, the adp 1877 resumes normal operation after the soft start sequence. figure 29. current limit hiccup mode, 20 a circuit
adp1877 rev. c | page 17 of 32 applications information setting the output voltage the output voltage is set using a resistive voltage divider from the output to fb. the voltage divider divides down the output voltage to the 0.6 v fb regulation voltage to set the regulation output voltage. the output voltage can be set to as low as 0.6 v and as high as 90% of the power input voltage. the maximum input bias current into fb is 100 na. for a 0.15% degradation in regulation voltage and with 100 na bias current, the low-side resistor, r bot , must be less than 9 k, which results in 67 a of divider current. for r bot , use a 1 k to 20 k resistor. a larger value resistor can be used but results in a reduction in output voltage accuracy due to the input bias current at the fb pin, while lower values cause increased quiescent current consumption. choose r top to set the output voltage by using the following equation: ? ? ? ? ? ? ? ? ? = fb fb out bot top v vv rr where: r top is the high-side voltage divider resistance. r bot is the low-side voltage divider resistance. v out is the regulated output voltage. v fb is the feedback regulation threshold, 0.6 v. the minimum output voltage is dependent on f sw and minimum dh on time. the maximum output voltage is dependent on f sw , the minimum dh off time, and the ir drop across the high-side n-channel mosfet (nmosfet) and the dcr of the inductor. for example, with an f sw of 600 khz (or 1.67 s) and minimum on time of 130 ns, the minimum duty cycle is approximately 7.8% (130 ns/1.67 s). if v in is 12 v and the duty cycle is 7.8%, then the lowest output is 0.94 v. as an example for the maximum output voltage, if v in is 5 v, f sw is 600 khz, and the minimum dh off time is 390 ns (330 ns dh off time plus approximately 60 ns total dead time), then the maximum duty cycle is 76%. therefore, the maximum output is approximately 3.8 v. if the ir drop across the high-side nmosfet and the dcr of the inductor is 0.5 v, then the absolute maximum output is 4.5 v (5 v ? 0.5 v), independent of f sw and duty cycle. soft start program the soft start by connecting a capacitor from ssx to agnd. the soft start function limits the input inrush current and prevents the output overshoot. on startup, a 6.5 a current source charges the ssx capacitor. the soft start period is approximated by ss ss c a v t = 5.6 6.0 the ssx pin reaches a final voltage equal to vcco. if the output voltage is precharged prior to turn-on, the adp1877 prevents reverse inductor current, which discharges the output capacitor. once the voltage at ssx exceeds the regulation voltage (typically 0.6 v), the reverse current is reenabled to allow the output voltage regulation to be independent of load current. when a controller is disabled, for instance, en1/en2 is pulled low or experiences an overcurrent limit condition, the soft start capacitor is discharged through an internal 1 k pull-down resistor. setting the current limit the current limit comparator measures the voltage across the low-side mosfet to determine the load current. the current limit is set by an external current limit resistor, r ilim . the current sense pin, ilimx, sources 50 a to this external resistor. this creates an offset voltage of r ilim multiplied by 50 a. when the drop across the low-side mosfet, r dson , is equal to or greater than this offset voltage, the adp1877 flags a current limit event. because the ilimx current and the mosfet, r dson , vary over process and temperature, the minimum current limit should be set to ensure that the system can handle the maximum desired load current. to do this, use the peak current in the inductor, which is the desired output current limit level plus ? of the ripple current, the maximum r dson of the mosfet at its highest expected temperature, and the minimum ilim current. a ri r max dson lpk ilim = 40 _ where: i lpk is the peak inductor current. the buck converters usually run a fairly high current. pcb layout and component placement may affect the current limit setting. an iteration of the r ilim value may be required for a particular board layout and mosfet selection. if alternative mosfets are substituted at some point in production, these resistor values may also need an iteration. keep in mind that the temperature coefficient of the mosfet, r dson , is typically 0.4%/ o c. accurate current limit sensing r dson of the mosfet can vary by more than 50% over the temperature range. accurate current limit sensing can be achieved by adding a current sense resistor from the source of the low-side mosfet to pgnd. make sure that the power rating of the current sense resistor is adequate for the application. apply the above equation and calculate r ilim by replacing r dson_max with r sense . the figure 31 illustrates the implementation of this accurate current limit sensing.
adp1877 rev. c | page 18 of 32 v in r ilim dhx dlx swx ilimx r sense adp1877 08299-008 figure 31. accurate current limit sensing setting the slope compensation in a current-mode control topology, slope compensation is needed to prevent subharmonic oscillations in the inductor current and to maintain a stable output. the external slope compensation is implemented by summing the amplified sense signal and a scaled voltage at the rampx pin. to implement the slope compensation, connect a resistor between rampx and the input voltage. the resistor, r ramp , is calculated by max dson cs ramp ra l r _ 10 106.3 = where: 3.6 10 10 is an internal parameter. l is the inductance of the inductor. r dson_max is the the low-side mosfet maximum on resistance. a cs is the gain, either 3 v/v, 6 v/v, 12 v/v, or 24 v/v, of the current sense amplifier (see the setting the current sense gain section for more details). keep in mind that r dson is temperature dependent and can vary as much as 0.4%/ o c. choose r dson at the maximum operating temperature. the voltage at rampx is fixed at 0.2 v, and the current going into rampx should be in between 6 a and 200 a. make sure that the following condition is satisfied: a200 v2.0 a6 ? ramp in r v for instance, with an input voltage of 12 v, r ramp should not exceed 1.9 m. if the calculated r ramp produces less than 6 a, then select a r ramp value that produces between 6 a and 20 a. figure 32 illustrates the connection of the slope compensation resistor r ramp and the current sense gain resistor r csg . v in r ilim dhx ramp dlx swx ilimx r csg adp1877 r ramp 08299-009 figure 32. slope compensation and cs gain connection setting the current sense gain the voltage drop across the external low-side mosfet is sensed by a current sense amplifier by multiplying the peak inductor current and the r dson of the mosfet. the result is then amplified by a gain factor of either 3 v/v, 6 v/v, 12 v/v, or 24 v/v, which is programmable by an external resistor, r csg , connected to the dl pin. this gain is sensed only during power-up and not during normal operation. the amplified voltage is summed with the slope compensation ramp voltage and fed into the pwm controller for a stable regulation voltage. the voltage range of the internal node, v cs , is between 0.4 v and 2.2 v. select the current sense gain such that the internal minimum amplified voltage (v csmin ) is above 0.4 v and the maximum amplified voltage (v csmax ) is 2.1 v. do not set v csmax above 2.1 v to account for temperature and part-to-part variations. note that v csmin or v csmax is not the same as v comp , which has a range of 0.75 v to 2.25 v. the following are equations for v csmin and v csmax : cs min dson lpp csmin a riv v ?= _ 2 1 75.0 cs max dson lpp loadmax csmax a ri iv v + += _ ) 2 1 (75.0 where: v csmin is the minimum amplified voltage of the internal current sense amplifier at zero output current. v csmax is the maximum amplified voltage of the internal current sense amplifier at maximum output current. r dson_min is the the low-side mosfet minimum on resistance. the zero-current level voltage of the current sense amplifier is 0.75 v. i lpp is the peak-to-peak ripple current in the inductor. i loadmax is the maximum output dc load current. table 6 shows the appropriate current sense gain settings for a given r dson maximum load current and a 33% inductor current ripple. because of the variation in r dson of the power mosfets (part-to-part variation and overtemperature) and the variation of the inductors, the users must verify that v comp does not exceed 2.2 v at the maximum output load current.
adp1877 rev. c | page 19 of 32 table 6. cs gain setting selection table for some popular configurations i lpp = 33% load acs = 3 acs = 6 acs = 12 acs = 24 r dson (m) load (a) v cs min (v) v cs max (v) v cs min (v) v cs max (v) v cs min (v) v cs max (v) v cs min (v) v cs max (v) 1.5 25 0.73 0.9 0.71 1.01 0.7 1.3 0.6 1.80 2 25 0.73 0.9 0.70 1.10 0.7 1.4 2 20 0.73 0.9 0.71 1.03 0.7 1.3 3 20 0.72 1.0 0.69 1.17 0.6 1.6 5 15 0.71 1.0 0.68 1.27 0.6 1.8 7 10 0.72 1.0 0.68 1.24 0.6 1.7 10 10 0.70 1.1 0.65 1.45 15 8 0.69 1.2 0.63 1.59 18 8 0.68 1.3 0.61 1.76 20 7 0.68 1.2 0.61 1.73 25 5 0.69 1.2 0.63 1.62 30 5 0.68 1.3 0.60 1.80 40 5 0.65 1.4 60 3 0.66 1.4 80 2 0.67 1.3 100 2 0.65 1.4 120 2 0.63 1.6 input capacitor selection the input current to a buck converter is a pulse waveform. it is zero when the high-side switch is off and approximately equal to the load current when it is on. the input capacitor carries the input ripple current, allowing the input power source to supply only the direct current. the input capacitor needs sufficient ripple current rating to handle the input ripple, as well as an esr that is low enough to mitigate input voltage ripple. for the usual current ranges for these converters, it is good practice to use two parallel capacitors placed close to the drains of the high-side switch mosfets (one bulk capacitor of sufficiently high current rating and a 10 f ceramic decoupling capacitor, typically). select an input bulk capacitor based on its ripple current rating. first, determine the duty cycle of the output. in out v v d = the input capacitor rms ripple current is given by )1( ddii o rms ?= where: i o is the output current. d is the duty cycle the minimum input capacitance required for a particular load is swesr o pp o minin fdriv ddi c ) ( )1( , ? ? = where: v pp is the desired input ripple voltage. r esr is the equivalent series resistance of the capacitor. if an mlcc capacitor is used, the esr is near 0, then the equation is simplified to sw pp o minin fv dd ic ? = )1( , the capacitance of mlcc is voltage dependent. the actual capacitance of the selected capacitor must be derated accordingly. in addition, add more bulk capacitance, such as by using electrolytic or polymer capacitors, as necessary for large step load transisents. make sure the current ripple rating of the bulk capacitor exceeds the minimum input current ripple of a particular design. input filter normally the input pin, vin, with a 0.1 f or greater value bypass capacitor to agnd, is sufficient for filtering out any unwanted switching noise. however, depending on the pcb layout, some switching noises can be passed down to the adp1877 internal circuitry; therefore, it is recommended to have a low pass filter at the vin pin. connecting a resistor, between 2 and 5 , in series with vin and a 1 f ceramic capacitor between vin and agnd creates a low pass filter that effectively filters out any unwanted glitches caused by the switching regulator. keep in mind that the input current could be larger than 100 ma when driving large mosfets. a 100 ma across a 5 resistor creates a 0.5 v drop, which is the same voltage drop in vcco. in this case, a lower resistor value is desirable.
adp1877 rev. c | page 20 of 3 2 vin adp1877 vin agnd 2 ? to 5 ? 1f 08299-010 figure 33. input fi lter configuration boost capacitor selection to lower system component count and cost, the adp1877 has a built-in rectifier (equivalent to the boost diode) between vcco and bstx. choose a boost ceramic capacitor with values between 0.1 f and 0.22 f, which provides the current for the high-side driver during switching. inductor selection the output lc filter smoothes the switched voltage at swx. choose an inductor value such that the inductor ripple current is approximately 1?3 of the maximum dc output load current. using a larger value inductor results in a physical size larger than required, and using a smaller value results in increased losses in the inductor and/or mosfet switches and larger voltage ripples at the output. choose the inductor value by the following equation: in out l sw out in v v if vv l where: l is the inductor value. f sw is the switching frequency. v out is the output voltage. v in is the input voltage. i l is the inductor ripple current, typically 1?3 of the maximum dc load current. output capacitor selection choose the output bulk capacitor to set the desired output voltage ripple. the impedance of the output capacitor at the switching frequency multiplied by the ripple current gives the output voltage ripple. the impedance is made up of the capacitive impedance plus the nonideal parasitic characteristics, the equivalent series resistance (esr), and the equivalent series inductance (esl). the output voltage ripple can be approximated with u u esl sw out sw esr l out lf cf riv 4 8 1 where: v out is the output ripple voltage. i l is the inductor ripple current. r esr is the equivalent series resistance of the output capacitor (or the parallel combination of esr of all output capacitors). l esl is the equivalent series inductance of the output capacitor (or the parallel combination of esl of all capacitors). solving c out in the previous equation yields esl sw l esr l out sw l out lfirivf i c 4 1 8 usually, the impedance is dominated by esr, such as in electrolytic or polymer capacitors, at the switching frequency, as stated in the maximum esr rating on the capacitor data sheet; therefore, output ripple reduces to esr l out riv electrolytic capacitors also have significant esl, on the order of 5 nh to 20 nh, depending on type, size, and geometry. pcb traces contribute some esr and esl, as well. however, using the maximum esr rating from the capacitor data sheet usually provides some margin such that measuring the esl is not usually required. in the case of output capacitors where the impedance of the esr and esl are small at the switching frequency, for instance, where the output cap is a bank of parallel mlcc capacitors, the capacitive impedance dominates and the output capacitance equation reduces to sw out l out fv i c 8 make sure that the ripple current rating of the output capacitors is greater than the maximum inductor ripple current. during a load step transient on the output, for instance, when the load is suddenly increased, the output capacitor supplies the load until the control loop has a chance to ramp the inductor current. this initial output voltage deviation results in a voltage droop or undershoot. the output capacitance, assuming 0 esr, required to satisfy the voltage droop requirement can be approximated by sw droop step out fv i c where: i step is the step load. v droop is the voltage droop at the output. when a load is suddenly removed from the output, the energy stored in the inductor rushes into the capacitor, causing the output to overshoot. the output capacitance required to satisfy the output overshoot requirement can be approximated by 2 2 2 ) ( out overshoot out step out v vv li c where: v overshoot is the overshoot voltage during the step load. select the largest output capacitance given by any of the previous three equations.
adp1877 rev. c | page 21 of 3 2 mosfet selection the choice of mosfet directly affects the dc-to-dc converter performance. a mosfet with low on resistance reduces i 2 r losses, and low gate charge reduces transition losses. the mosfet should have low thermal resistance to ensure that the power dissipated in the mosfet does not result in excessive mosfet die temperature. the high-side mosfet carries the load current during on time and usually carries most of the transition losses of the converter. typically, the lower the on resistance of the mosfet, the higher the gate charge and vice versa. therefore, it is important to choose a high-side mosfet that balances the two losses. the conduction loss of the high-side mosfet is determined by the equation ? ? ? ? ? ? ? ? ? in out dson load c v v rip 2 )( where: r dson is the mosfet on resistance. the gate charging loss is approximated by the equation swg pv g fqvp ? where v pv is the gate driver supply voltage. q g is the mosfet total gate charge. note that the gate charging power loss is not dissipated in the mosfet but rather in the adp1877 internal drivers. this power loss should be taken into consideration when calculating the overall power efficiency. the high-side mosfet transition loss is approximated by the equation 2 )( sw fr load in t fttiv p + ? where: p t is the high-side mosfet switching loss power. t r is the rise time in charging the high-side mosfet. t f is the fall time in discharging the high-side mosfet. t r and t f can be estimated by rise driver gsw r i q t _ ? fall driver gsw f i q t _ ? where: q gsw is the gate charge of the mosfet during switching and is given in the mosfet data sheet. i driver_rise and i driver_fall are the driver current put out by the adp1877 internal gate drivers. if q gsw is not given in the data sheet, it can be approximated by 2 gs gd gsw q qq +? where: q gd and q gs are the gate-to-drain and gate-to-source charges given in the mosfet data sheet. i driver_rise and i driver_fall can be estimated by gate source on sp dd rise driver r r vv i + ? ? _ _ gate sinkon sp fall driver r r v i + ? _ _ where: v dd is the input supply voltage to the driver and is between 2.75 v and 5 v, depending on the input voltage. v sp is the switching point where the mosfet fully conducts; this voltage can be estimated by inspecting the gate charge graph given in the mosfet data sheet. r on_source is the on resistance of theadp1877 internal driver, given in table 1 , when charging the mosfet. r on_sink is the on resistance of the adp1877 internal driver, given in table 1 , when discharging the mosfet. r gate is the on gate resistance of mosfet given in the mosfet data sheet. if an external gate resistor is added, add this external resistance to r gate . the total power dissipation of the high-side mosfet is the sum of conduction and transition losses: t chs ppp + ? the synchronous rectifier, or low-side mosfet, carries the inductor current when the high-side mosfet is off. the low- side mosfet transition loss is small and can be neglected in the calculation. for high input voltage and low output voltage, the low-side mosfet carries the current most of the time. therefore, to achieve high efficiency, it is critical to optimize the low-side mosfet for low on resistance. in cases where the power loss exceeds the mosfet rating or lower resistance is required than is available in a single mosfet, connect multiple low-side mosfets in parallel. the equation for low-side mosfet conduction power loss is ? ? ? ? ? ? ?? in out dson load cls v v rip 1 )( 2 there is also additional power loss during the time, known as dead time, between the turn-off of the high-side switch and the turn-on of the low-side switch, when the body diode of the low- side mosfet conducts the output current. the power loss in the body diode is given by osw df bodydiode iftv p = where: v f is the forward voltage drop of the body diode, typically 0.7 v. t d is the dead time in the adp1877, typically 30 ns when driving some medium-size mosfets with input capacitance of approximately 3 nf.
adp1877 rev. c | page 22 of 32 then the power loss in the low-side mosfet is bodydiode cls ls ppp += note that mosfet, r dson , increases with increasing temperature with a typical temperature coefficient of 0.4%/ o c. the mosfet junction temperature rise over the ambient temperature is t j = t a + ja p d where: ja is the thermal resistance of the mosfet package. t a is the ambient temperature. p d is the total power dissipated in the mosfet. loop compensation as with most current mode step-down controller, a transcon- ductance error amplifier is used to stabilize the external voltage loop. compensating the adp1877 is fairly easy; an rc compensator is needed between comp and agnd. figure 34 shows the configuration of the compensation components: r comp , c comp , and cc2. because c c2 is very small compared to c comp , to simplify calculation, c c2 is ignored for the stability compensation analysis. compx adp1877 agnd c comp r comp c c2 0.6v fbx g m 08299-011 figure 34. compensation components the open loop gain transfer function at angular frequency, s, is given by )()( )( szsz v v ggsh filter comp out ref cs m = (1) where: g m is the transconductance of the error amplifer, 500 s. g cs is the tranconductance of the current sense amplifier. z comp is the impedance of the compensation network. z f ilter is the impedance of the output filter. v ref = 0.6 v g cs with units of a/v is given by min dson cs cs ra g _ 1 = (2) where: a cs is the current sense gain of either 3 v/v, 6 v/v, 12 v/v, or 24 v/v set by the gain resistor between dl and pgnd. r dson_min is the the low-side mosfet minimum on resistance. because the zero produced by the esr of the output capacitor is not needed to stabilize the control loop, the esr is ignored for analysis. then z filter is given by out filter sc z 1 = (3) because c c2 is very small relative to c comp , z comp can be written as comp comp comp comp comp comp sc c sr sc rz + = += 1 1 (4) at the crossover frequency, the open loop transfer function is unity of 0 db, h (f cross ) = 1. combining equation 1 and equation 3, z comp at the crossover frequency can be written as ) )( 2 ()( ref out out cs m cross cross comp v vc gg f fz = (5) the zero produced by r comp and c comp is comp comp zero cr f = 2 1 (6) at the crossover frequency, equation 4 can be shown as cross zero cross comp cross comp f ff rfz + = )( (7) combining equations 5 and equation 7 and solving for r comp gives ) () 2 ( ref out out cs m cross zero cross cross comp v vc gg f ff f r + = (8) choose the crossover and zero frequencies as follows: 13 sw cross f f = (9) 655 sw cross zero ff f == (10) substituting equation 2, equation 9, and equation 10 into equation 8 yields ) () 2 ( 83.0 ref out out m cross dson cs comp v vc g f ra r = (11) where: g m is the transconductance of the error amplifer, 500 s. a cs is the current sense gain of 3 v/v, 6 v/v, 12 v/v or 24 v/v. r dson is on resistance of the low-side mosfet. v ref = 0.6 v and combining equation 6 and equation 10 yields cross comp comp fr c = 2 (12) and lastly set c c2 to comp c comp c cc ?? 10 1 20 1 2 (13)
adp1877 rev. c | page 23 of 3 2 switching noise and overshoot reduction in any high speed step-down regulator, high frequency noise (generally in the range of 50 mhz to 100 mhz) and voltage overshoot are always present at the gate, the switch node (sw), and the drains of the external mosfets. the high frequency noise and overshoot are caused by the parasitic capacitance, c gd , of the external mosfet and the parasitic inductance of the gate trace and the packages of the mosfets. when the high current is switched, electromagnetic interference (emi) is generated, which can affect the operation of the surrounding circuits. to reduce voltage ringing and noise, it is required to add an rc snubber between sw and pgnd for applications with more than 10 a output current, as illustrated in figure 35 . snubbers may also be needed in applications where the duty cycle in one of the channels is higher than or equal to 50%. in most applications, r snub is typically 2 to 4 , and c snub typically 1.2 nf to 3 nf. r snub can be estimated by oss mosfet snub c l r 2 ? and c snub can be estimated by oss snub cc ? where : l mosfet is the total parasitic inductance of the high-side and low-side mosfets, typically 3 nh, and is package dependent. c oss is the total output capacitance of the high-side and low- side mosfets given in the mosfet data sheet. the size of the rc snubber components need to be chosen correctly to handle the power dissipation. the power dissipated in r snub is sw snub in snub fcvp = 2 in most applications, a component size 0805 for r snub is sufficient. however, the use of an rc snubber reduces the overall efficiency, generally by an amount in the range of 0.1% to 0.5%. the rc snubber cannot reduce the voltage overshoot. a resistor, shown as r rise in figure 35 , at the bstx pin helps to reduce overshoot and is generally between 2 and 4 . adding a resistor in series, typically between 2 and 4 , with the gate driver also helps to reduce overshoot. if a gate resistor is added, then r rise is not needed. dh1 sw1 ilim1 dl1 pgnd1 m2 m1 l vout coutx r snub c snub r rise bst1 vdl r ilim1 adp1877 (channel 1) vin 08299-012 figure 35. application circuit with a snubber voltage tracking the adp1877 includes a tracking feature that tracks a master voltage. this feature is especially important when the adp1877 is powering separate power supply voltages on a single integrated circuit, such as the core and i/o voltages of a dsp or microcon- troller. in these cases, improper sequencing can cause damage to the load. in all tracking configurations, the output can be set as low as 0.6 v for a given operating condition. the soft start time setting of the master voltage should be longer than the soft start of the slave voltage. this forces the rise time of the master voltage to be imposed on the slave voltage. if the soft start setting of the slave voltage is longer, the slave comes up more slowly, and the tracking relationship is not seen at the output. two tracking configurations are possible with the adp1877: coincident and ratiometric trackings. full time ddr termination is not recommended when using these tracking features. coincident tracking the most common application is coincident tracking, used in core vs. i/o voltage sequencing and similar applications. coincident tracking limits the slave output voltage to be the same as the master voltage until it reaches regulation. connect the slave trk input to a resistor divider from the master voltage that is the same as the divider used on the slave fb pin. this forces the slave voltage to be the same as the master voltage. for coincident tracking, use r trkt = r top and r trkb = r bot , as shown in figure 37 . time slave voltage master voltage voltage (v) 08299-013 figure 36. coincident tracking c ss1 100nf c ss2 20nf 3.3 v v out1_master fb1 en r bot 10k? fb2 ss1 adp1877 en1 en2 ss2 v cco trk1 trk2 r top 20k ? 1.8v v out2_slave r trkb 10k ? r trkt 20k? 1.1v 10k ? 45.3k ? 08299-014 1m ? figure 37. example of a coincident tracking circuit
adp1877 rev. c | page 24 of 3 2 ratiometric tracking the ratio of the slave output voltage to the master voltage is a function of the two dividers. ratiometric tracking limits the output voltage to a fraction of the master voltage. for ratiometric tracking, the simplest configuration is to tie the trk pin of the slave channel to the fbx pin of the master channel. however, because of the large internal offset between trkx and fbx, this ratiometric tracking configuration is not recommended. a tracking configuration that requires the trkx voltage of the slave channel below 0.6 v is not recommended because of the large internal trkx to fbx offset voltage. ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? + = trkb trkt bot top master out slave out r r r r v v 1 1 _ _ as the master voltage rises, the slave voltage rises identically. eventually, the slave voltage reaches its regulation voltage, where the internal reference takes over the regulation while the trkx input continues to increase and thus removes itself from influencing the output voltage. another ratiometric tracking configuration is having the slave channel rise more quickly than the master channel, as shown in figure 38 and figure 39 . the tracking circuits in figure 37 and figure 38 are virtually identical with the exception that rtrkb > rtrkt, as shown in figure 38 . to ensure that the output voltage accuracy is not compromised by the trkx pin being too close in voltage to the 0.6 v reference, make sure that the final value of the trkx voltage of the slave channel is at least 0.7 v. c ss1 100nf c ss2 20nf 3.3 v v out1_master fb1 en r bot 10k fb2 ss1 adp1877 en1 en2 ss2 vcco trk1 trk2 r top 20k 1.8v v out2_slave r trkb 10k r trkt 5k 2.2v 10k 45.3k 0 8299-015 1m figure 38. a simple ratiometric tracking circuit (slave channel has a faster ramp rate) time slave voltage master v olta g e voltage (v) 08299-016 figure 39. ratiometric tracking (slave channel has a faster ramp rate)
adp1877 rev. c | page 25 of 32 pcb layout guideline in any switching converter, there are some circuit paths that carry high di/dt, which can create spikes and noise. some circuit paths are sensitive to noise, while other circuits carry high dc current and can produce significant ir voltage drops. the key to proper pcb layout of a switching converter is to identify these critical paths and arrange the components and the copper area accordingly. when designing pcb layouts, be sure to keep high current loops small. in addition, keep compensation and feedback comp onents away from the switch nodes and their associated components. the following is a list of recommended layout practices for the synchronous buck controller, arranged by decreasing order of importance. mosfets, input bulk capacitor, and bypass capacitor the current waveform in the top and bottom fets is a pulse with very high di/dt; therefore, the path to, through, and from each individual fet should be as short as possible, and the two paths should be commoned as much as possible. in designs that use a pair of d-pak or a pair of so-8 fets on one side of the pcb, it is best to counter-rotate the two so that the switch node is on one side of the pair, and the high-side drain can be bypassed to the low side source with a suitable ceramic bypass capacitor, placed as close as possible to the fets. this minimizes the inductance around this loop through the fets and capacitor. the recommended bypass ceramic capacitor values range from 1 f to 22 f, depending upon the output current. this bypass capacitor is usually connected to a larger value bulk filter capacitor and should be grounded to the pgndx plane. high current and current sense paths part of the adp1877 architecture is sensing the current across the low-side fet between the swx and pgndx pins. the switching gnd currents of one channel creates noise and can be picked up by the other channel. it is essential to keep the sw1/sw2 and pgnd1/pgnd2 traces as short as possible and placed very close to the fets to achieve accurate current sensing. the following schematic illustrates the proper connection technique for the sw1/sw2, pgnd1/pgnd2, and pgndx plane. note that pgnd1 and pgnd2 are only jointed at the pgnd plane. adp1877 dh1 sw1 m2 l1 v out1 v in m1 pgnd plane cout1 cin1 c decouple1 m3 l2 v out2 vin m4 cout2 cin2 c decouple2 23 24 21 22 19 20 17 18 pgnd2 dl2 sw2 dh2 dl1 pgnd1 08299-017 figure 40. grounding technique for two channels signal paths the negative terminals of agnd, vin bypass, compensation components, soft start capacitor, and the bottom end of the output feedback divider resistors should be tied to an almost isolated small agnd plane. these connections should attach from their respective pins to the agnd plane; these connections should be as short as possible. no high current or high di/dt signals should be connected to this agnd plane. the agnd area should be connected through one wide trace to the negative terminal of the output filter capacitors. pgnd plane the pgndx pin handles a high di/dt gate drive current returning from the source of the low side mosfet. the voltage at this pin also establishes the 0 v reference for the overcurrent limit protection function and the ilimx pin. a pgnd plane should connect the pgndx pin and the vdl bypass capacitor, 1 f, through a wide and direct path to the source of the low side mosfet. the placement of cin is critical for controlling ground bounce. the negative terminal of cin must be placed very close to the source of the low-side mosfet. feedback and current limit sense paths avoid long traces or large copper areas at the fbx and ilimx pins, which are low signal level inputs that are sensitive to capacitive and inductive noise pickup. it is best to position any series resistors and capacitors as close as possible to these pins. avoid running these traces close and/or parallel to high di/dt traces.
adp1877 rev. c | page 26 of 3 2 switch node the switch node is the noisiest place in the switcher circuit with large ac and dc voltages and currents. this node should be wide to keep resistive voltage drop down. to minimize the generation of capacitively coupled noise, the total area should be small. place the fets and inductor close together on a small copper plane to minimize series resistance and keep the copper area small. gate driver paths gate drive traces (dh and dl) handle high di/dt and tend to produce noise and ringing. they should be as short and direct as possible. if possible, avoid using feedthrough vias in the gate drive traces. if vias are needed, it is best to use two relatively large ones in parallel to reduce the peak current density and the current in each via. if the overall pcb layout is less than optimal, slowing down the gate drive slightly can be very helpful to reduce noise and ringing. it is occasionally helpful to place small value resistors, such as between 2 and 4 , on the dh and dl pins. these can be populated with 0 resistors if resistance is not needed. note that the added gate resistance increases the switching rise and fall times as well as switching power loss in the mosfet. output capacitors the negative terminal of the output filter capacitors should be tied close to the source of the low side fet. doing this helps to minimize voltage differences between agnd and pgndx.
adp1877 rev. c | page 27 of 3 2 typical operating circuits vcco vcco vcco 845k ? en1 sync 100nf to vin 845k ? vin vcco vdl agnd freq en2 sw1 dh1 pgnd1 dl1 dl2 pgnd2 dh2 sw2 trk2 fb2 comp2 ramp2 ss2 pgood2 ilim2 bst2 trk1 fb1 comp1 ramp1 ss1 pgood1 ilim1 bst1 adp1877 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 66.5k ? 47pf 330p f 36.5k ? 47pf 680pf 100nf 1f 0.1f 0.1f 1f 1f r ilim2 4k ? l2 m4 m3 r csg2 4k ? cout 22 cout 21 cin2 v out2 1.8v 10a vin = 10v to 14v, or can be connected to a separate power supply 5v r ilim1 4k ? l1 m2 m1 r csg1 4k ? cout 12 cout 11 cin1 v out1 3.3v 10a vin = 10v to 14v r top2 20k? r bot2 10k? cin1, cin2: 10f/x7r/25v/1210 2, grm32dr71e106ka12, murata cout 11 , cout 21 : 330f/6.3v/poscap 2, 6tpf330m9l, sanyo cout 12 , cout 22 : 22f/x5r/0805/6.3v, grm21br60j226me39, murata f sw = 600khz l1, l2: 1.2h, wurth elektronik, 744325120 m1, m2, m3, m4: irlr7821 r top1 45.3k ? r bot1 10k ? 2 ? 08299-019 1m ? 1m ? figure 41. typical medium current operating circuit
adp1877 rev. c | page 28 of 32 vcco vcco vcco 845k ? en1 sync 100nf to vin 845k ? vin vcco vdl agnd freq en2 sw1 dh1 pgnd1 dl1 dl2 pgnd2 dh2 sw2 trk2 fb2 comp2 ramp2 ss2 pgood2 ilim2 bst2 trk1 fb1 comp1 ramp1 ss1 pgood1 ilim1 bst1 adp1877 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 18.7k ? 220pf 2.2n f 12.7k ? 220pf 3.9nf 100nf 1f 0.1f 0.1f 1f 1f r ilim2 3.7k ? r dh2 3 ? l2 m4 m3 r csg2 22k ? cout 22 cout 21 cin2 v out2 1.05v 20a vin r ilim1 3.7k ? l1 m2 m1 r csg1 22k ? cout 12 1.2nf 4 ? cout 11 cin1 cin v out1 1.8v 20a vin = 10v to 14v r top2 7.5k ? r bot2 10k? cin1, cin2: 10f/x7r/25v/1210 2, grm32dr71e106ka12, murata cout 11 , cout 21 : 680f/2.5v/poscap 2, 2r5tpd680m5, sanyo cout 12 , cout 22 : 22f/x5r/0805/6.3v 3, grm21br60j226me39, murata f sw = 300khz cin = 180f/20v, 20sp180m, oscon, sanyo l1, l2: 1.3h, wurth elektronik, 7443551130 m1, m3: bsc080n03ls m2, m4: bsc030n03ls r top1 20k ? r bot1 10k ? 2 ? 1.2nf 4 ? 08299-020 r dh1 3 ? r dl1 3 ? r dl2 3 ? 1m ? 1m ? figure 42. typical 20 a operating circuit
adp1877 rev. c | page 29 of 3 2 vcco 84.5k ? vcco 698k ? en1 sync 100nf to vin 698k ? vin vcco vdl agnd freq en2 sw1 dh1 pgnd1 dl1 dl2 pgnd2 dh2 sw2 trk2 fb2 comp2 ramp2 ss2 pgood2 ilim2 bst2 trk1 fb1 comp1 ramp1 ss1 pgood1 ilim1 bst1 adp1877 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 22.6k ? 68pf 820p f 8.25k ? 120pf 2.2nf 100nf 1f 0.1f 0.1f 1f 1f r ilim2 2.8k ? l2 m2b m2a r csg2 22k ? cout2 cin2 v out2 1.8v 5a vin r ilim1 2.8k ? l1 m1b m1a r csg1 22k ? cout1 cin1 v out1 5v 5a vin = 10v to 14v r top2 20k? r bot2 10k? cin1, cin2: 10f/x5r/16v/1206 2, grm31cr61c106ka88, murata m1, m2: si4944dy or bson03md cout1: 22f/x5r/1210/6.3v 3, grm32dr60j226ka01, murata cout2: 22f/x5r/1210/6.3v 3, grm32dr60j226ka01, murata f sw = 750khz l1: 2h, 744310200, wurth elektronik l2: 1.15h, 744310115, wurth elektronik r top1 73.2k ? r bot1 10k ? 3 ? 08299-021 1m ? 1m ? figure 43. typical low current operating circuit
adp1877 rev. c | page 30 of 3 2 vcco 78.7k ? vcco 121k ? en1 sync 100nf to vin 121k ? vin vcco vdl agnd freq en2 sw1 dh1 pgnd1 dl1 dl2 pgnd2 dh2 sw2 trk2 fb2 comp2 ramp2 ss2 pgood2 ilim2 bst2 trk1 fb1 comp1 ramp1 ss1 pgood1 ilim1 bst1 adp1877 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 5.34k ? 33pf 1.8n f 8.66k ? 33pf 1nf 100nf 1f 0.1f 0.1f 1f 1f r ilim2 4.99k ? l2 m4 m3 r csg2 47k ? cout2 cin2 v out2 1.8v 1.8a vin r ilim1 4.99k ? l1 m2 m1 r csg1 47k ? cout1 cin1 v out1 1.05v 1.8a vin = 3v to 5.5v cin1, cin2: 4.7f/x5r/16v/0805 2, grm219r60j475ke19, murata m1, m2, m3, m4: si2302ads, sot23 cout1, cout2: 22f/x5r/0805/6.3v, grm21br60j226me39, murata f sw = 800khz l1, l2: 1h, d62lcb1r0m, toko 5 ? 08299-022 r top2 20k? r bot2 10k? r top1 73.2k ? r bot1 10k ? 1m ? 1m ? figure 44. typical low current application with v in < 5.5 v
adp1877 rev. c | page 31 of 3 2 outline dimensions compliant to jedec standards mo-220-whhd. 112408-a 1 0.50 bsc bottom view top view pin 1 indi c ator 32 9 16 17 24 25 8 exposed pad p i n 1 i n d i c a t o r 3.65 3.50 sq 3.45 eating plane 0.05 max 0.02 nom 0.20 ref coplanarity 0.08 0.30 0.25 0.18 5.10 5.00 sq 4.90 0.80 0.75 0.70 for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. 0.50 0.40 0.30 0.25 min s figure 45. 32-lead lead frame chip scale package [lfcsp_vq] 5 mm 5 mm body, very thin quad (cp-32-11) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ADP1877ACPZ-R7 ?40c to +85c 32-lead lead frame chip scale package [lfcsp_vq] cp-32-11 adp1877hc-evalz evaluation board with 13 a output 1 z = rohs compliant part.
adp1877 rev. c | page 32 of 32 notes ?2009C2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08299-0-4/10(c)

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